1. Field of the Invention
The present invention relates to a CMOS logic circuit element, a semiconductor device, manufacturing method thereof and to a method of designing a semiconductor circuit used in the manufacturing method. More specifically, the present invention relates to a CMOS logic circuit device, a semiconductor device, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method enabling higher speed of operation and reduced power consumption and preventing degradation of electrical characteristics, even when the devices are miniaturized.
2. Description of the Background Art
Higher degree of miniaturization, higher speed of operation and lower power consumption have been increasingly desired in semiconductor devices such as represented by CMOS logic circuit devices and DRAMs (Dynamic Random Access Memory). To meet such demands, developments have been made in improving transistor performance, reduction in parasitic capacitance of interconnection layers and reduction of line resistance.
FIG. 19 is a schematic cross section representing a multi-layered interconnection structure of a semiconductor device related to the present invention. Referring to FIG. 19, in the semiconductor device, on a first interlayer insulating film 146a, a first interconnection 145a of aluminum is formed. On the first interconnection 145a, second interconnections 145b to 145d of aluminum are formed with a second interlayer insulating film 146b interposed. On second interconnections 145b to 145d, a third interconnection 145e is formed with a second interlayer insulating film 146b. On the third interconnection 145e, a third interlayer insulating film 146c is formed. Here, second interconnections 145b to 145d are formed to extend in a direction approximately orthogonal to the direction of extension of the first and third interconnections 145a and 145e. 
Referring to FIG. 19, as the semiconductor devices have been miniaturized, a space S between interconnections becomes smaller. As the space S between interconnections becomes smaller, total parasitic capacitance Ctot (hereinafter referred to as total capacitance) of interconnection 145c has been increasing. Here, the total capacitance Ctot is represented as the total sum of parasitic capacitance Cc formed between interconnections 145b and 145d adjacent in horizontal direction, parasitic capacitance Ctop formed between interconnections 145e and 145c, and parasitic capacitance Cbot formed between interconnections 145a and 145c. When the space S between interconnections is made small, the ratio of parasitic capacitance Cc with respect to total capacitance Ctot attains as high as about 80%.
Therefore, conventionally, in order to reduce the parasitic capacitance Cc between interconnections in the horizontal direction, a proposal has been made to place an insulator having relatively low dielectric constant such as a silicon oxide film to which fluorine added (SiOF) between adjacent interconnections, so as to reduce parasitic capacitance Cc in the horizontal direction.
The insulator having low dielectric constant such as SiOF, however, involves larger amount of leakage current as compared with the conventionally used silicon oxide film and, further, it suffers from the problem of high reactivity with the material such as aluminum of interconnections 145a to 145e. Accordingly, a multi-layered interconnection structure of a semiconductor device such as shown in FIG. 20 has been proposed.
FIG. 20 is a schematic cross section showing another example of the multi-layered interconnection structure of a semiconductor device related to the present invention. Referring to FIG. 20, the semiconductor device basically has the similar structure as the semiconductor device of FIG. 19. In the semiconductor device shown in FIG. 20, however, surfaces of second interconnections 145b to 145d are covered by portions 157a to 157c of the interlayer insulating film, which are parts of the conventional interlayer insulating film 146b of silicon oxide. Insulators 156a to 156d having low dielectric constant such as SiOF, having lower dielectric constant than silicon oxide film constituting the interlayer insulating film 146b, are arranged between interconnections 145b to 145d. On second interlayer insulating film 146b and insulators 156a to 156d of low dielectric constant, an interlayer insulating film 146d of silicon oxide is formed.
In this manner, as insulators 156a to 156d having low dielectric constant are arranged between interconnections 145b to 145d, parasitic capacitance Cc in the horizontal direction of interconnection 145c can be effectively reduced. Further, as portions 157a to 157c of interlayer insulating film formed of silicon oxide are formed between interconnections 145b to 145d and insulators 156a to 156d of low dielectric constant, direct contact between interconnections 145b to 145d with insulators 156a to 156d of low dielectric constant can be prevented. Therefore, reaction between interconnections 145b to 145d and insulators 156a to 156d having low dielectric constant can be prevented. Accordingly, degradation of electrical characteristics of the semiconductor device caused by fluctuation of electrical characteristics of interconnections 145b to 145d can be prevented.
While the semiconductor devices has been miniaturized with the parasitic capacitance of interconnections reduced, cross sectional area of the interconnection itself has been reduced, as the semiconductor devices has been miniaturized. Smaller cross sectional area of the interconnection leads to increased line resistance, which causes degradation of electrical characteristic such as slower speed of operation of the semiconductor device, which is a significant problem. For this reason, use of copper having lower resistance as the material of interconnection in place of conventionally used aluminum, has been studied. When copper is used as the material of the interconnection, line resistance can be decreased even when the interconnection has the same cross sectional area as the aluminum interconnection. Accordingly, higher speed of operation and lower power consumption of the semiconductor device can be attained.
In Damascene process used generally in forming copper interconnection, a silicon nitride film or the like is used as an etching stopper in the process. The silicon nitride film remains in the interlayer insulating film even after the copper interconnection is completed. Here, the silicon nitride film has higher dielectric constant than the silicon oxide film which has been conventionally used as the interlayer insulating film. Therefore, in view of parasitic capacitance of interconnections, sometimes the total capacitance Ctot attains higher than in the conventional example, when copper interconnection is formed. The inventors have found that, as a result, it is difficult to obtain a semiconductor device having superior electrical characteristics and allowing higher speed of operation and lower power consumption simply by replacing the conventional aluminum interconnection with copper interconnection.
When the interconnection is formed using copper, a barrier metal layer is formed on the surface of the interconnection, in order to prevent diffusion of copper to the interlayer insulating film. Here, the barrier metal layer must have a minimum film thickness to maintain its function. Generally, a material for the barrier metal layer has higher electrical resistance than copper. As the semiconductor devices have been miniaturized, the ratio of barrier metal layer with respect to the cross sectional area of the interconnection increases, and therefore influence of the barrier metal layer on the line resistance comes to be non-negligible. Line resistance may be out of the designed range because of variation in film thickness of the barrier metal layer. The inventors have also found that this leads to the problem of degraded electrical characteristics of the semiconductor device.
One object of the present invention is to provide a semiconductor device including an interconnection structure having superior electrical characteristics allowing higher speed of operation and lower power consumption even when the device is miniaturized.
Another object of the present invention is to provide a CMOS logic circuit device including an interconnection structure having superior electrical characteristics allowing higher speed of operation and lower power consumption even when miniaturized.
A further object of the present invention is to provide a method of manufacturing a semiconductor device including an interconnection structure having superior electrical characteristics allowing higher speed of operation and lower power consumption even when miniaturized.
A still further object of the present invention is to provide a method of designing a semiconductor circuit used in the method of manufacturing the semiconductor device including an interconnection structure having superior electrical characteristics allowing higher speed of operation and lower power consumption even when miniaturized.
The semiconductor device according to the aforementioned one aspect of the present invention includes a semiconductor substrate, a conductive region, a first interconnection layer, a first insulator, a second interconnection layer and a second insulator. The semiconductor substrate has a main surface. The conductive region is formed on the main surface of the semiconductor substrate. First interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. The first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. The second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having lower electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer. The second insulator is formed to surround the second interconnection layer and has higher dielectric constant than the first insulator.
Here, in the first interconnection layer having relatively short line length such as a short interconnection within a circuit block, for example, it is necessary to reduce the distance between interconnections as small as possible, as the degree of integration of the circuit elements is increased. When the distance between interconnections is reduced, reduction in parasitic resistance between interconnections is particularly effective in improving the speed of operation of the semiconductor device.
In the semiconductor device in accordance with one aspect of the present invention, as a first insulator having relatively low dielectric constant is formed to surround a first interconnection layer having relatively short line length, parasitic resistance between interconnections of the first interconnection layer can be made smaller than the parasitic resistance between interconnections of the second interconnection layer. As a result, the speed of operation of the semiconductor device can effectively be improved. Therefore, a semiconductor device having such an interconnection structure that ensures superior electrical characteristics can be obtained.
Further, the second interconnection layer which has longer line length than the first interconnection layer contains material having low electrical resistance than the material contained in the first interconnection layer, and therefore the line resistance of the second interconnection layer can be made lower than that of the first interconnection layer. Here, in the second interconnection layer which corresponds to the long line such as interconnections between circuit blocks, reduction in line resistance is more effective in improving the speed of operation of the semiconductor device. Therefore, the semiconductor device in accordance with one aspect of the present invention enables higher speed of operation.
Further, by reducing line resistance, power consumption of the semiconductor device can be reduced. As a result, a semiconductor device having such an interconnection structure that ensures superior electrical characteristics can be obtained.
In the semiconductor device in accordance with the above described one aspect, the second and the first interconnection layers may be formed on different layers on the main surface of the semiconductor substrate.
Here, as the first and second interconnection layers of mutually different line lengths are formed in different layers, the interconnection structure in the semiconductor device can be simplified as compared when the first and second interconnection layers of different line lengths are formed in one layer.
When the first and second interconnection layers are formed in different layers in this manner, an insulator in one layer can be formed by one material, even when the first and second insulators are to be formed by different materials. Therefore, it is possible to form the first and second insulators through the same process steps as in the conventional process for forming insulators. Therefore, the steps of manufacturing the semiconductor device are not complicated. As a result, the number of steps for manufacturing the semiconductor device is not increased, and therefore increase in cost in manufacturing the semiconductor device can be prevented.
In the semiconductor device in accordance with the above described one aspect, the second interconnection layer may be formed in a layer upper than the layer in which the first interconnection layer is formed.
In this case, the first interconnection layer having relatively short line length is formed at a region closer to the elements on the semiconductor substrate. The second interconnection layer corresponding to the long distance interconnection for connecting circuit blocks is formed upper than the first interconnection layer, and therefore the interconnection path of the second interconnection layer can be miniaturized without much adverse influence of the arrangement of the first interconnection layer. Therefore, total line length can be reduced than when the first interconnection layer is formed upper than the second interconnection layer. As a result, higher speed of operation and lower power consumption of the semiconductor device can be attained.
In the semiconductor device in accordance with the above described one aspect, the second insulator may be positioned above and below the second interconnection layer.
In the semiconductor device in accordance with the above described one aspect, the first interconnection layer may include aluminum, and the second interconnection layer may include copper.
Here, copper has lower electrical resistance than the conventional interconnection material of aluminum, and has longer electro migration life. Further, the material cost is lower and is superior as an interconnection material. As the second interconnection layer contains copper, higher speed of operation and lower power consumption of the semiconductor device can be ensured.
Further, as the first interconnection layer contains aluminum, the manufacturing apparatuses and processes for forming the conventional aluminum interconnection can be used directly, when the first interconnection layer is formed. Therefore, the semiconductor device in accordance with the present invention can be manufactured easily.
In the semiconductor device in accordance with the above described one aspect, the second insulator may contain a silicon nitride film.
The silicon nitride film may be used as an etching stopper in the Damascene process for forming the second interconnection layer containing copper. Therefore, the second interconnection layer containing copper can be readily formed.
In the semiconductor device in accordance with the above described one aspect, the first insulator may include a silicon oxide film.
In the semiconductor device in accordance with the above described one aspect, cross sectional area of the second interconnection layer may be the same or larger than the cross sectional area of the first interconnection layer.
Here, when the second interconnection layer corresponding to the long distance interconnection such as the line for connecting circuit blocks is adapted to have larger cross sectional area than the first interconnection layer, line resistance of the second interconnection layer can further be reduced. Therefore, higher speed of operation and lower power consumption of the semiconductor device can be attained.
In the semiconductor device in accordance with the above described one aspect, the first interconnection layer may include third and fourth interconnection layers, and the second interconnection layer may include fifth and sixth interconnection layers. The distance between the fifth and sixth interconnection layers may be the same or longer than the distance between the third and fourth interconnection layers.
Here, in the second interconnection layer corresponding to the long distance interconnection such as the line for connecting circuit blocks, the distance between interconnections may be made larger than in the first interconnection layer, and therefore parasitic resistance between lines in the second interconnection layer can surely be reduced. As a result, higher speed of operation of the semiconductor device can be attained.
In the semiconductor device in accordance with the above described first aspect, the second interconnection layer may have one side surface and the other side surface positioned opposite to the one side surface, and barrier metal layers may be formed on one and the other side surfaces. Total film thickness BM of the barrier metal layer may be selected to satisfy the relation of BMmin/Wxe2x89xa6BM/Wxe2x89xa61xe2x88x92(K/(Kxe2x88x921))xc3x97xcex94W/W, where W represents set line width of the second interconnection layer in a direction approximately vertical to the one side surface, BM represents total film thickness of the barrier metal layer formed on the one and the other side surfaces, BMmin represents minimum necessary film thickness of the barrier metal layer and K represents tolerable rate of increase in resistance of the second interconnection layer when the set line width W is decreased by xcex94W.
Here, line resistance R of a portion having the length 1 of a conductive line of uniform property with uniform cross sectional area S is given by the following equation (1), where xcfx81 represents specific resistance.
When the thickness of the second interconnection layer is represented by T, resistance per unit length of the second interconnection layer is given by the following equation (2).
The resistance per unit length when the set line width W of the second interconnection layer is decreased by xcex94W is represented by the following equation (3).
As the tolerable rate of increase of the resistance of the second interconnection layer when the set line width W is decreased by xcex94W is given by K, the second interconnection layer must satisfy the relation represented by the expression (4). The expression can be transformed to expression (5).
As the minimum necessary film thickness of the barrier metal layer is BMmin, the total film thickness BM of the barrier metal layer must also satisfy the relation represented by the expression (6).
As a result, if the total film thickness BM of the barrier metal layer is determined to satisfy the relation of expression (7), it becomes possible. for the barrier metal layer to exhibit its function and for the rate of increase in resistance of the second interconnection layer to be not higher than the tolerable ratio K.                     R        =                              L            S                    xc3x97          ρ                                    (        1        )                                ρ                              (                          W              -              BM                        )                    xc3x97          T                                    (        2        )                                ρ                              (                          W              -                              Δ                ⁢                                  xe2x80x83                                ⁢                W                            -              BM                        )                    xc3x97          T                                    (        3        )                                          ρ                                    (                              W                -                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  W                                -                BM                            )                        xc3x97            T                          ≦                  K          xc3x97                      ρ                                          (                                  W                  -                  BM                                )                            xc3x97              T                                                          (        4        )                                          BM          W                ≦                  1          -                                    K                              K                -                1                                      xc3x97                                          Δ                ⁢                                  xe2x80x83                                ⁢                W                            W                                                          (        5        )                                                      BM            ⁢                          xe2x80x83                        ⁢            min                    W                ≦                  BM          W                                    (        6        )                                                      BM            ⁢                          xe2x80x83                        ⁢            min                    W                ≦                  BM          W                ≦                  1          -                                    K                              K                -                1                                      xc3x97                                          Δ                ⁢                                  xe2x80x83                                ⁢                W                            W                                                          (        7        )            
In the semiconductor device in accordance with the above described one aspect, the second interconnection layer has a bottom surface on which a bottom barrier metal layer is formed. Film thickness BMT of the bottom barrier metal layer may be selected to satisfy the relation of BMminxe2x89xa6BMT/Txe2x89xa61xe2x88x92(KT/(KTxe2x88x921))xc3x97xcex94T/T, where T represents set film thickness of the second interconnection layer in a direction approximately vertical to the bottom surface, BMT represents film thickness of the bottom barrier metal layer, BMTmin represents minimum necessary film thickness of the bottom barrier metal layer and KT represents tolerable rate of increase in resistance of the second interconnection layer when the set film thickness T is decreased by xcex94T.
In this case also, as in the method of determining the total film thickness BM of the barrier metal layer described above, in order for the rate of increase in resistance of the second interconnection layer to be not higher than the tolerable rate of increase KT when the set film thickness T of the second interconnection layer is decreased by xcex94T, the film thickness BMT of the bottom barrier metal layer must be selected to satisfy the relation given by the expression (8). The expressions described above can be transformed to expression (9) below.
As the minimum necessary film thickness of the bottom barrier metal layer is BMTmin, the film thickness BMT of the bottom barrier metal layer must also satisfy the relation represented by the expression (10).
As a result, if the film thickness BMT of the barrier metal layer is determined to satisfy the relation (11), it is possible for the bottom barrier metal layer to exhibit necessary function and for the rate of increase in resistance of the second interconnection layer to be not higher than the tolerable rate of increase KT.                               ρ                                    (                              W                -                BM                            )                        xc3x97                          (                              T                -                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  T                                -                BMT                            )                                      ≦                  KT          xc3x97                      ρ                                          (                                  W                  -                  BM                                )                            xc3x97                              (                                  T                  -                  BMT                                )                                                                        (        8        )                                          BMT          T                ≦                  1          -                                    KT                              KT                -                1                                      xc3x97                                          Δ                ⁢                                  xe2x80x83                                ⁢                T                            T                                                          (        9        )                                                      BMT            ⁢                          xe2x80x83                        ⁢            min                    W                ≦                  BMT          T                                    (        10        )                                                      BMT            ⁢                          xe2x80x83                        ⁢            min                    T                ≦                  BMT          T                ≦                  1          -                                    KT                              KT                -                1                                      xc3x97                                          Δ                ⁢                                  xe2x80x83                                ⁢                T                            T                                                          (        11        )            
In a method of designing a semiconductor circuit in accordance with another aspect of the present invention is to design a semiconductor device including a first interconnection layer having relatively short line length, a first insulator formed to surround the first interconnection layer, a second interconnection layer having longer line length than the first interconnection layer and a second insulator formed to surround the second interconnection layer, and the method includes the following steps. A first interconnection structure pattern including a plurality of interconnection layers having a prescribed distance between interconnection lines and containing a specified material, and an insulator formed to surround each of the plurality of interconnection layers and containing a specified material is prepared. A second interconnection structure pattern including a plurality of interconnection layers having approximately the same distance between interconnection lines as the distance between interconnection lines of the first interconnection structure pattern and containing a specific material, and an insulator formed to surround each of the plurality of interconnection layers and containing a specific material is prepared. In the first interconnection structure pattern, a first parasitic capacitance of each interconnection layer is calculated. In the second interconnection structure pattern, a second parasitic capacitance for each interconnection layer is calculated. The material of the interconnection layer of the first or second interconnection structure pattern having smaller one of the first and second parasitic capacitances is selected as a material to be contained in the first interconnection layer. A material of the insulator in the first or second interconnection structure pattern having smaller one of the first and second parasitic capacitances is selected as a material to be contained in the first insulator.
Accordingly, it is possible to provide a semiconductor circuit having smaller parasitic capacitance in the first interconnection layer of which reduction in parasitic capacitance is effective in improving speed of operation of the semiconductor device. As a result, higher speed of operation of the semiconductor device can readily be attained. Accordingly, a semiconductor device having an interconnection structure of superior electrical characteristics can be obtained.
The method of designing a semiconductor circuit in accordance with the above described another aspect may further includes the following steps. The first line resistance of each interconnection layer in the first interconnection structure pattern is calculated. The second line resistance of each interconnection layer of the second interconnection structure pattern is calculated. By multiplexing the first parasitic capacitance and the first line resistance, a first evaluation value is calculated for the first interconnection structure pattern. By multiplexing the second parasitic capacitance and the second line resistance in the second interconnection structure pattern, a second evaluation value is calculated. The material of the interconnection layer of the first or second interconnection structure patterns having smaller one of the first and second evaluation values is used as the material to be contained in the second interconnection layer. The material of the insulator in the first or second interconnection structure pattern having smaller one of the first and second evaluation value is selected as a material to be contained in the second insulator.
Here, a semiconductor circuit having a small evaluation value for the second interconnection layer can readily be obtained. Here, the second interconnection layer has longer line length than the first interconnection layer, and corresponds to the lines for connecting circuit blocks. In the second interconnection layer having relatively long line length, it is effective to improve speed of operation and lower power consumption of the semiconductor device to reduce the evaluation value obtained by multiplexing the parasitic capacitance and the line resistance. Therefore, a semiconductor device adapted to improve speed of operation and to reduce power consumption can readily be obtained.
In the method of designing a semiconductor circuit in accordance with the above described another aspect, the first and second interconnection structure patterns may be one selected from the group consisting of an interconnection structure pattern using aluminum as the material of the interconnection layer, an interconnection structure pattern using copper as the material of the interconnection layer, and an interconnection structure pattern using copper as the material of the interconnection layer with film thickness of the interconnection layer being determined to attain approximately the same line resistance as the interconnection layer of the interconnection structure pattern using aluminum as the material of the interconnection layer.
Here, higher speed of operation and lower power consumption can readily be attained in a semiconductor circuit using, as a material of the interconnection layer, aluminum or copper.
In the method of designing a semiconductor circuit in accordance with the above described another aspect, the distance between interconnections may be approximately the same as the minimum processing dimension in the step of photolithography used in manufacturing a semiconductor device.
In the method of manufacturing a semiconductor device in accordance with a further aspect of the present invention, the method of designing a semiconductor circuit in accordance with the above described another aspect is utilized.
Therefore, even when miniaturized, a semiconductor device attaining higher speed of operation and lower power consumption can readily be obtained.
The semiconductor device in accordance with a still further aspect of the present invention includes an interconnection layer and a barrier metal layer. The interconnection layer has one side surface and the other side surface positioned opposite to the one side surface. The barrier metal layer is formed on the one side surface and the other side surface. Total film thickness BM of the barrier metal layer is selected to satisfy the relation of BMmin/Wxe2x89xa6BM/Wxe2x89xa61xe2x88x92(K/(Kxe2x88x921))xc3x97xcex94W/W, where W represents set line width of the interconnection layer in a direction approximately vertical to the one side surface, BM represents total film thickness of the barrier metal layer formed on the one side surface and the other side surface, BMmin represents minimum necessary film thickness of the barrier metal layer and K represents tolerable rate of increase in resistance of the interconnection layer when the set line width W is decreased by xcex94W.
Therefore, as in the semiconductor device in accordance with the above described one aspect, the total film thickness BM of the barrier metal layer is selected to satisfy the above described relation, and therefore the function of the barrier metal layer is surely exhibited, and the ratio of increase in the line resistance can be made not higher than the tolerable ratio of increase K. Therefore, increase in line resistance to be higher than that tolerable ratio of increase K can surely be prevented. As a result, degradation of electrical characteristics such as lower speed of operation of the semiconductor device caused by the increased line resistance can surely be prevented.
In the semiconductor device in accordance with the above described still further aspect, the interconnection layer has a bottom surface on which a bottom barrier metal layer is formed. Total film thickness BMT of the bottom barrier metal layer may be selected to satisfy the relation of BMmin/Txe2x89xa6BMT/Txe2x89xa61xe2x88x92(KT/(KTxe2x88x921))xc3x97xcex94T/T, where T represents set film thickness of the interconnection layer in a direction approximately vertical to the bottom surface, BMT represents film thickness of the bottom barrier metal layer, BMTmin represents minimum necessary film thickness of the bottom barrier metal layer and KT represents tolerable rate of increase in resistance of the interconnection layer when the set film thickness T is decreased by xcex94T.
In this case, as in the semiconductor device in accordance with the above described one aspect, the total film thickness BMT of the bottom barrier metal layer is selected to satisfy the above described relation. Therefore, the barrier metal layer surely exhibits its functions and the rate of increase in the resistance of interconnection layer can be made not higher than the tolerable rate of increase KT.
A CMOS (Complementary Metal Oxide Semiconductor) logic circuit device in accordance with a still further aspect of the present invention includes a semiconductor substrate, a conductive region, a first interconnection layer, a first insulator, a second interconnection layer and a second insulator. The semiconductor substrate has a main surface. The conductive region is formed on the main surface of the semiconductor substrate. The first interconnection layer is electrically connected to the conductive region, has a relatively short line length and contains a material having relatively high electrical resistance. The first insulator is formed to surround the first interconnection layer and has relatively low dielectric constant. The second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having lower electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer. The second insulator is formed to surround the second interconnection layer and has higher dielectric constant than the first insulator.
Therefore, the CMOS logic circuit device in accordance with the still further aspect provides similar effects as provided by the semiconductor device in accordance with the above described one aspect, as the logic circuit device has similar structure as the semiconductor device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.